Technical mental model
Interrupt priority on Cortex-M is subtle because numeric priority fields are only meaningful after accounting for implemented bits and grouping behavior. Deterministic response needs explicit priority design.
Key low-level points:
- Priority encoding is hardware-specific; not all bits are implemented on every part.
- Masking controls (
BASEPRI,PRIMASK) alter who can preempt whom. - Latency is shaped by both handler duration and nesting policy.
Equations and constraints that drive decisions
Simplified response-time model:
Where:
- : remaining time of active handler if non-preemptible
Implementation walkthrough
Map criticality classes first, then assign priorities systematically.
Keep high-priority handlers short and defer heavy work to lower-priority context.
Test nested interrupt scenarios under realistic load.
Record latency metrics rather than relying on intuition.
Validation and debugging checklist
Do not rely on raw priority numbers without considering bit implementation.
Global masking as a default strategy causes unpredictable latency growth.
ISR code should avoid blocking and long loops.
Priority plan should be documented alongside safety/timing rationale.
A good priority design lets you predict interrupt ordering before running, then confirm it with measurement.
